Z8 Encore! XP® F08xA Seriess
Product Specification
91
devices on the multi-node network. The following three MULTIPROCESSOR modes are
available in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0]in the UART Control 1 Register. For all mul-
tiprocessor modes, bit MPENof the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01bto MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. Each new incoming byte
interrupts the CPU. The software is responsible for determining the end of the frame. It
checks for the end-of-frame by reading the MPRXbit of the UART Status 1 Register for
each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame
is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter-
rupts to go inactive until the next address byte. If the new frame’s address matches the
UART’s, the data in the new frame is processed as well.
The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s
address into the UART Address Compare Register. This mode introduces additional hard-
ware control, interrupting only on frames that match the UART’s address. When an
incoming address byte does not match the UART’s address, it is ignored. All successive
data bytes in this frame are also ignored. When a matching address byte occurs, an inter-
rupt is issued and further interrupts now occur on each succesive data byte. When the first
data byte in the frame is read, the NEWFRMbit of the UART Status 1 Register is asserted.
All successive data bytes have NEWFRM=0. When the next address byte occurs, the hard-
ware compares it to the UART’s address. If there is a match, the interrupts continues and
the NEWFRMbit is set for the first byte of the new frame. If there is no match, the UART
ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11band by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame remains accompanied by a NEWFRMassertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This fea-
ture reduces the software overhead associated with using a GPIO pin to control the trans-
ceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as illustrated in Figure 13. The Driver Enable signal asserts
when a byte is written to the UART Transmit Data register. The Driver Enable signal
PS024705-0405
P R E L I M I N A R Y
UART
ZILOG [ ZILOG, INC. ]
