Z8 Encore! XP® 4K Series
Product Specification
127
010 = Reserved
011 = Reserved
100 = Differential, unbuffered input
101 = Differential, buffered input with unity gain
110 = Reserved
111 = Reserved
ADC Data High Byte Register
The ADC Data High Byte (ADCD_H) register contains the upper eight bits of the ADC
output. The output is an 13-bit two’s complement value. During a single-shot conversion,
this value is invalid. Access to the ADC Data High Byte register is read-only. Reading the
ADC Data High Byte register latches data in the ADC Low Bits register.
Table 74. ADC Data High Byte Register (ADCD_H)
7
6
5
4
3
2
1
0
BITS
ADCDH
F72H
FIELD
RESET
R/W
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
ADDR
ADCDH—ADC Data High Byte
This byte contains the upper eight bits of the ADC output. These bits are not valid during a
single-shot conversion. During a continuous conversion, the most recent conversion out-
put is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Byte (ADCD_L) register contains the lower bits of the ADC output
as well as an overflow status bit. The output is a 13-bit two’s complement value. During a
single-shot conversion, this value is invalid. Access to the ADC Data Low Byte register is
read-only. Reading the ADC Data High Byte register latches data in the ADC Low Bits
register.
Table 75. ADC Data Low Bits Register (ADCD_L)
7
6
5
4
3
2
1
0
OVF
X
BITS
ADCDL
Reserved
FIELD
RESET
R/W
X
R
X
R
X
R
X
R
X
R
X
R
X
R
R
F73H
ADDR
PS022815-0206
Analog-to-Digital Converter
ZILOG [ ZILOG, INC. ]
