Z8 Encore! XP® 4K Series
Product Specification
22
Reset Sources
Table 10 lists the possible sources of a system reset.
Table 10. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Special Conditions
NORMAL or HALT
modes
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level
None
Watch-Dog Timer time-out
when configured for Reset
RESET pin assertion
All reset pulses less than three system clocks
in width are ignored.
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger
(OCDCTL[0] set to 1) is unaffected by the reset
STOP mode
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level
RESET pin assertion
All reset pulses less than the specified analog
delay are ignored. See Table 134 on page 219
DBG pin driven Low
None
Power-On Reset
Z8 Encore! XP® 4K Series devices contain an internal power-on reset (POR) circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this timeout is longer.
After the Z8 Encore! XP® 4K Series device exits the Power-On Reset state, the eZ8 CPU
fetches the Reset vector. Following Power-On Reset, the PORstatus bit in the Watch-Dog
Timer Control (WDTCTL) register is set to 1.
Figure 5 illustrates Power-On Reset operation. Refer to the Electrical Characteristics on
page 212 for the POR threshold voltage (VPOR).
PS022815-0206
Reset, STOP Mode Recovery and Low Voltage Detection
ZILOG [ ZILOG, INC. ]
