Z8 Encore! XP® 4K Series
Product Specification
206
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
ER
ER
R
src
ER
IM
C
Z
S
V
D
SUBX dst, src
dst ← dst – src
28
29
F0
F1
62
63
64
65
66
67
68
69
72
73
74
75
76
77
78
79
F2
*
*
*
*
1
*
4
4
2
2
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
3
3
2
3
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
6
SWAP dst
dst[7:4] ↔ dst[3:0]
X
–
*
*
*
*
X
0
–
–
–
–
IR
r
TCM dst, src
(NOT dst) AND src
r
Ir
r
R
R
R
IR
R
IM
IM
ER
IM
r
IR
ER
ER
r
–
–
*
*
*
*
0
0
–
–
–
–
TCMX dst, src
(NOT dst) AND src
TM dst, src
dst AND src
r
Ir
R
R
R
IR
R
IM
IM
ER
IM
Vector
IR
ER
ER
TMX dst, src
TRAP Vector
dst AND src
–
–
*
*
0
–
–
–
–
–
SP ← SP – 2
@SP ← PC
–
–
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
5F
–
–
–
–
–
–
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
