Z8 Encore! XP® 4K Series
Product Specification
204
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
OR dst, src
dst ← dst OR src
42
43
44
45
46
47
48
49
50
51
D8
–
*
*
0
–
–
2
2
3
3
3
3
4
4
2
2
3
3
4
3
4
3
4
3
3
2
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
ORX dst, src
POP dst
dst ← dst OR src
–
–
*
*
0
–
–
–
–
–
dst ← @SP
SP ← SP + 1
–
–
IR
ER
POPX dst
PUSH src
dst ← @SP
SP ← SP + 1
–
–
–
–
–
–
–
–
–
–
–
–
SP ← SP – 1
@SP ← src
R
70
71
2
2
3
2
3
2
IR
IM
IF70
PUSHX src
SP ← SP – 1
@SP ← src
ER
C8
–
–
–
–
–
–
3
2
RCF
RET
C ← 0
CF
AF
0
–
–
–
–
–
–
–
–
–
–
–
1
1
2
4
PC ← @SP
SP ← SP + 2
RL dst
R
90
91
*
*
*
*
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
RLC dst
R
10
11
*
*
*
*
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
