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Z8F021APH020SC 参数 Datasheet PDF下载

Z8F021APH020SC图片预览
型号: Z8F021APH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采! XP -R 4K系列高性能8位微控制器 [Z8 Encore! XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® 4K Series  
Product Specification  
118  
Programmable Trigger Point Alarm  
The ADC contains two programmable trigger values, defined in the ADC High Threshold  
(ADCTHH) Register (Table 76 on page 128) and the ADC Low Threshold (ADCTLH)  
Register (Table 77 on page 128). Each of these values is 8 bits and is NOT a two’s com-  
plement number. The alarm is intended for single-ended operation and so the alarm values  
reflect positive numbers only. Both thresholds have independent control and status bits.  
When the ADC is enabled and the ADC value exceeds the high threshold, an ADC inter-  
rupt is asserted and the high threshold status bit is set. When enabled and the ADC value is  
less than the low threshold, an ADC interrupt is asserted and the low threshold status bit is  
set.  
Because the alarm value is positive it is compared to the most significant 8 data bits of the  
ADC value, excluding the sign bit. The ADC alarm bits are compared to  
{ADCD_H[6:0],ADCD_L[7]}. Alternatively, the alarm value is compared to the ADC  
value shifted left by one bit. Negative ADC values never trigger the high alarm and always  
trigger the low alarm. Because the ADC output is software compensated for offset, nega-  
tive (pre-compensated) values can occur in SINGLE-ENDED mode.  
The alarm is primarily intended for use in CONTINUOUS mode so that the CPU can  
determine threshold crossings without servicing interrupts for all ADC samples. If used in  
SINGLE-SHOT mode, the ADC will only interrupt the CPU if the single sample triggers  
an alarm.  
The alarm status bits are updated on each conversion, regardless of the alarm enable bit  
values. The alarm enable bits only determine whether or not an interrupt is generated.  
Interrupts  
The ADC is able to interrupt the CPU under three conditions:  
When a conversion has been completed  
When the 8 Most Significant Bits of a sample exceed the programmable high threshold  
ADCTHH[7:0]  
When the 8 Most Significant Bits of a sample is less than the programmable low threshold  
ADCTLH[7:0]  
The conversion interrupt occurs when the ADC is enabled and both alarms are disabled.  
When either or both alarms are enabled, the conversion interrupt is disabled and only the  
alarm interrupts may occur.  
When the ADC is disabled, none of the three sources can cause an interrupt to be asserted;  
however, an interrupt pending when the ADC is disabled is not cleared.  
The three interrupt events share a common CPU interrupt. The interrupt service routine  
must query the ADC Control/Status (ADCCTL1) Register to determine the cause of an  
PS022815-0206  
Analog-to-Digital Converter