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Z8F021APH020SC 参数 Datasheet PDF下载

Z8F021APH020SC图片预览
型号: Z8F021APH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采! XP -R 4K系列高性能8位微控制器 [Z8 Encore! XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® 4K Series  
Product Specification  
117  
3. Write the ADC Control/Status Register 1 to configure the ADC  
Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode, as  
well as unbuffered or buffered mode.  
If the alarm function is required, set ALMHENand/or ALMLEN.  
Write the REFSELHbit of the pair {REFSELH, REFSELL} to select the internal  
voltage reference level or to disable the internal reference. The REFSELLbit is  
contained in the ADC Control Register 0.  
4. Write to the ADC Control Register 0 to configure the ADC for continuous conversion.  
The bit fields in the ADC Control register may be written simultaneously:  
Write to the ANAIN[3:0]field to select from the available analog input sources  
(different input pins available depending on the device)  
Set CONTto 1 to select continuous conversion.  
If the internal VREF must be output to a pin, set the REFEXTbit to 1. The internal  
voltage reference must be enabled in this case.  
Write the REFSELLbit of the pair {REFSELH, REFSELL} to select the internal  
voltage reference level or to disable the internal reference. The REFSELHbit is  
contained in ADC Control/Status Register 1.  
Set CENto 1 to start the conversions.  
5. When the first conversion in continuous operation is complete (after 5129 system  
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic  
performs the following operations:  
CENresets to 0 to indicate the first conversion is complete. CENremains 0 for all  
subsequent conversions in continuous operation.  
An interrupt request is sent to the Interrupt Controller to indicate the conversion is  
complete.  
6. The ADC writes a new data result every 256 system clock cycles. For each completed  
conversion, the ADC control logic performs the following operations:  
Writes the 13-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:3]}.  
If the high and low alarms are disabled, sends an interrupt request to the Interrupt  
Controller denoting conversion complete.  
If the high alarm is enabled and the ADC value is higher than the alarm threshold,  
generates an interrupt.  
If the low alarm is enabled and the ADC value is lower than the alarm threshold,  
generates an interrupt.  
7. To disable continuous conversion, clear the CONTbit in the ADC Control Register  
to 0.  
PS022815-0206  
Analog-to-Digital Converter