Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port with multiplexed Address (A7-A0) and
Data (D7-D0) ports. These eight I/O lines can be pro-
grammed as inputs or outputs or can be configured under
software control as an Address/Data port for interfacing
external memory. The input buffers are Schmitt-triggered
and the output buffers can be globally programmed as ei-
ther push-pull or open-drain. Low EMI output buffers can
be globally programmed by the software. Port 1 can be
placed under handshake control. In this configuration, Port
3, lines P33 and P34 are used as the handshake controls
RDY1 and /DAV1 (Ready and Data Available). To inter-
face external memory, Port 1 must be programmed for the
multiplexed Address/Data mode. If more than 256 external
locations are required, Port 0 outputs the additional lines
(Figure 19).
1
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z86E40 to
share common resources in multiprocessor and DMA ap-
plications.
Port 2 (I/O)
MCU
Handshake Controls
/DAV1 and RDY1
(P33 and P34)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R
500 kΩ
Figure 19. Port 1 Configuration (Z86E40 Only)
DS97Z8X0500
P R E L I M I N A R Y
27
ZILOG [ ZILOG, INC. ]
