Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Additional Timing Table
T = -40 °C to +105 °C
A
1
16 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Units
Conditions
Notes
1
Input Clock Period
3.5V
5.5V
62.5
62.5
DC
DC
ns
ns
1,7,8
1,7,8
2
TrC,TfC
TwC
Clock Input Rise &
Fall Times
3.5V
5.5V
15
15
ns
ns
1,7,8
1,7,8
3
Input Clock Width
3.5V
5.5V
31
31
ns
ns
1,7,8
1,7,8
4
TwTinL
TwTinH
TpTin
Timer Input Low
Width
3.5V
5.5V
70
70
ns
ns
1,7,8
1,7,8
5
Timer Input High
Width
3.5V
5.5V
5TpC
5TpC
1,7,8
1,7,8
6
Timer Input Period
3.5V
5.5V
8TpC
8TpC
[1,7,8
1,7,8
7
TrTin, TfTin Timer Input Rise
& Fall Timer
3.5V
5.5V
100
100
ns
ns
1,7,8
1,7,8
8A
8B
9
TwIL
TwIL
TwIH
Twsm
Int. Request Low
Time
3.5V
5.5V
70
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
3.5V
5.5V
5TpC
5TpC
1,3,7,8
1,3,7,8
Int. Request Input
High Time
3.5V
5.5V
5TpC
1,2,7,8
10
STOP Mode
Recovery Width
Spec
3.5V
5.5V
12
12
ns
ns
4,8
4,8
11
12
Tost
Oscillator Startup
Time
3.5V
5.5V
5TpC
5TpC
4,8
4,8
Twdt
Watch-Dog Timer
Delay Time
3.5V
5.5V
10
5
ms
ms
D0 = 0
D1 = 0
5,11
5,11
Before Timeout
3.5V
5.5V
20
10
ms
ms
D0 = 1
D1 = 0
5,11
5,11
3.5V
5.5V
40
20
ms
ms
D0 = 0
D1 = 1
5,11
5,11
3.5V
5.5V
160
80
ms
ms
D0 = 1
D1 = 1
5,11
5,11
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode Delay is on
5. Reg. WDTMR
6. The VCC voltage spec. of 5.5V guarantees 5.0V +/- ± 0.5V
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using
XTAL divide-by-one mode.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
10. Standard Mode (not Low EMI output ports)
11. Using internal RC
DS97Z8X0500
P R E L I M I N A R Y
23
ZILOG [ ZILOG, INC. ]
