Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Additional Timing Table (Divide-By-One Mode)
T = 0 °C to +70 °C
T
= -40 °C to +105 °C
A
A
1
4 MHz
4 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Min
Max
Units
Notes
1
Input Clock Period
3.5V
5.5V
250
250
DC
DC
250
250
DC
DC
ns
ns
1,7,8
1,7,8
2
3
4
5
6
7
TrC,TfC
TwC
Clock Input Rise &
Fall Times
3.5V
5.5V
25
25
25
25
ns
ns
1,7,8
1,7,8
Input Clock Width
3.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
TwTinL
TwTinH
TpTin
Timer Input Low
Width
3.5V
5.5V
100
70
100
70
ns
ns
1,7,8
1,7,8
Timer Input High
Width
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,7,8
1,7,8
Timer Input Period
3.5V
5.5V
8TpC
8TpC
8TpC
8TpC
1,7,8
1,7,8
TrTin, TfTin Timer Input Rise
& Fall Timer
3.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
8A TwIL
8B TwIL
Int. Request Low
Time
3.5V
5.5V
100
70
100
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,3,7,8
1,3,7,8
9
TwIH
Int. Request Input
High Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,2,7,8
1,2,7,8
10
Twsm
STOP Mode
Recovery Width
Spec
3.5V
5.5V
12
12
12
12
ns
ns
4,8
4,8
11
Tost
Oscillator Startup
Time
3.5V
5.5V
5TpC
5TpC
5TpC
4,8,9
Notes:
1. Timing Reference uses 0.7 V for a logic 1 and 0.2 V for a logic 0.
CC
2. Interrupt request via Port 3 (P31-P33).
3. Interrupt request via Port 3 (P30).
4. SMR-D5 = 1, POR STOP Mode Delay is on.
5. Reg. WDTMR.
CC
6. The V voltage specification of 5.5V guarantees 5.0V ±+/- 0.5V and
CC
the V voltage specification of 3.5V guarantees 3.5V only.
CC
7. SMR D1 = 0.
8. Maximum frequency for internal system clock is 4 MHz when
using XTAL divide-by-one mode.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
DS97Z8X0500
P R E L I M I N A R Y
21
ZILOG [ ZILOG, INC. ]
