Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
T = 0°C to 70°C
A
16 MHz
Note [3]
V
No
Symbol
TdA(AS)
Parameter
Min
Max
Units
Notes
CC
1
Address Valid to /AS Rise
Delay
3.5V
5.5V
25
25
ns
ns
2
2
3
4
5
6
7
8
9
TdAS(A)
TdAS(DR)
TwAS
/AS Rise to Address Float
Delay
3.5V
5.5V
35
35
ns
ns
2
/AS Rise to Read Data
Req’d Valid
3.5V
5.5V
180
180
ns
ns
1,2
2
/AS Low Width
3.5V
5.5V
40
40
ns
ns
TdAS(DS)
TwDSR
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
3.5V
5.5V
0
0
ns
ns
3.5V
5.5V
135
135
ns
ns
1,2
1,2
1,2
2
TwDSW
3.5V
5.5V
80
80
ns
ns
TdDSR(DR)
ThDR(DS)
/DS Fall to Read Data Req’d
Valid
3.5V
5.5V
75
75
ns
ns
Read Data to /DS Rise Hold
Time
3.5V
5.5V
0
0
ns
ns
10 TdDS(A)
/DS Rise to Address Active
Delay
3.5V
5.5V
50
50
ns
ns
2
11 TdDS(AS)
12 TdR/W(AS)
13 TdDS(R/W)
14 TdDW(DSW)
15 TdDS(DW)
16 TdA(DR)
/DS Rise to /AS Fall Delay
3.5V
5.5V
35
35
ns
ns
2
R//W Valid to /AS Rise
Delay
3.5V
5.5V
25
25
ns
ns
2
/DS Rise to R//W Not Valid
3.5V
5.5V
35
35
ns
ns
2
Write Data Valid to /DS Fall
(Write) Delay
3.5V
5.5V
55
55
25
25
ns
ns
2
/DS Rise to Write Data Not
Valid Delay
3.5V
5.5V
35
35
ns
ns
2
Address Valid to Read Data
Req’d Valid
3.5V
5.5V
230
230
ns
ns
1,2
2
17 TdAS(DS)
18 TdDM(AS)
20 ThDS(AS)
/AS Rise to /DS Fall Delay
3.5V
5.5V
45
45
ns
ns
/DM Valid to /AS Fall Delay
3.5V
5.5V
30
30
ns
ns
2
/DS Valid to Address Valid
Hold Time
3.5V
5.5V
35
35
ns
ns
Notes:
1. When using extended memory timing add 2 TpC
2. Timing numbers given are for minimum TpC
3. The V voltage specification of 5.5V guarantees 5.0V +/- ±0.5V and
CC
the V voltage specification of 3.5V guarantees 3.5V only
CC
Standard Test Load
All timing references use 0.7 V for a logic 1 and 0.2 V for a logic 0
CC
CC
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
18
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
