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Z8601720ASC 参数 Datasheet PDF下载

Z8601720ASC图片预览
型号: Z8601720ASC
PDF下载: 下载PDF文件 查看货源
内容描述: PCMCIA接口方案 [PCMCIA Interface Solution]
分类和应用: 总线控制器微控制器和处理器外围集成电路PC时钟
文件页数/大小: 138 页 / 1062 K
品牌: ZILOG [ ZILOG, INC. ]
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Z86017/Z16017 PCMCIA Interface Solution  
Product Specification  
68  
EEPROM Register  
Address: SELECT 28h  
Name: ATA/IDE Dual Drive Control  
Type: Read/Write  
Bit Placement Bit Name  
Description  
Bit 0  
M_S_enable  
This bit enables the Master/Slave mode control. When  
this bit is set to 1, the Master/Slave function is enabled.  
When it is set to 0, this function is disabled.  
When programmed, this bit determines when to drive the  
ATA/IDE bus. When set to 1, the ZX6017 drives the  
ATA bus when the host writes a 1 into Bit 4 of the  
“Drive/Head” task file register. Both primary and  
secondary addresses are compared. If this bit is set to 0,  
then the ZX6017 drives the bus if the host writes a 0 into  
Bit 4 of the “Drive/Head” task fie register.1  
Unused  
Bit 1  
Drive_select  
Bit 7-2  
Reserved  
NOTES:  
1. Read Back Values: Z86017 00010000b = 10h  
Z16017 00100000b = 20h  
EEPROM Register  
Address: SELECT 2Ah  
Name: Power Management Timer Count Value  
Type: Read/Write  
Table 52. Power Management Timer Count Value: Address 2Ah  
Bit Placement Bit Name  
Description  
Power management timer count value. The timer reset  
Bit 7-0  
TIMER_VAL  
during all PCMCIA activity. When the timer expires, it  
powers down all noncritical signals. TIMER intervals  
(sec.) = PC_MCLK (sec.) * 2(27) * timer_val. For  
example: PC_MCLK (20 MHz, 50 ns) * 2(27) * 1 = 6.67  
sec. Also see Register 2Ch (Table 56).  
PS012002-1201  
Programming Internal Registers  
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