Z86017/Z16017 PCMCIA Interface Solution
Product Specification
69
EEPROM Register
Address: SELECT 2Bh
Name: Power Management Control Register
Type: Read/Write
Table 53. Power Management control Register: Address 2Bh
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
EN_8BIT_MODE
When set to 1, this bit enables the 8-bit mode on the local
interface. When cleared, it enables the 16-bit interface.
EN_MODEM_ALT
EN_CLK
When set to 1, this bit enables the alternate modem
functions/pins. When cleared, it disables modem functions.
When this bit is set to 1, all internal clocks are disabled
after loading from the serial EEPROM. When this bit is
cleared, all clocks are enabled.
Bit 3
Bit 4
EN_PADS1
EN_TIMER
When this bit is set to 1, the PCMCIA external pads are
powered-down, unless PCMCIA(*) PC_HCE1 and
PC_HCE2 are active. When this bit is cleared, all external
pads are enabled.
When this bit is set to 1, the power management timer is
enabled. The timer value is contained in Register 2A.
When this bit is cleared, the power management timer is
held reset and disabled.
Bit 5
Bit 6
EN_PM_RDY
EN_EXT_PD
When this bit is set to 1, the ZX6017 sets BUSY on the
PCMCIA interface when the host sets the power down bit
in CCR1.
When this bit is set to 1, the power management timer
activates the external power down signal EXTP_PWND.
When this bit is cleared, the external signal is not be
activated. See also Register 0Bh (Table 67).
Bit 7
EN_EXPD_POL
When this bit is set to 1, the external power down signal
EXTP_PWND is active Low. When this bit is cleared,
EXTP_PWND is active High.
NOTES:
1. When the En_Pads bit is set, access to the CCR Registers is disabled.
Programming Internal Registers
PS012002-1201
ZILOG [ ZILOG, INC. ]
