Z86017/Z16017 PCMCIA Interface Solution
Product Specification
38
Table 12. Master Clock
EEPROM
CLK
Timing
Interrupt
Pulse1Width Comments
Register 0
Bit 1
Register 0
Bit 9
Clock In
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50 ns
50 ns
50 ns
50 ns
100 ns
100 ns
100 ns
100 ns
6.4 µs
3.2 µs
800 ns
200 ns
12.8 µs
6.4 µs
1.6 µs
400 ns
204 µs
102 µs
25 µs
5.25 µs
404 µs
204 µs
50 µs
Recommended
12.5 µs
Recommended
NOTES:
1. The pulse width of the /PC.IREQ signal in pulse mode is dependent on the clock period of the master clock input (TPMCKIN). The pulse
width of the /PC.IREQ signal is equal to 192 x TPMCKIN.
PS012002-1201
Programming Internal Registers
ZILOG [ ZILOG, INC. ]
