Z86017/Z16017 PCMCIA Interface Solution
Product Specification
36
EEPROM REGISTER
EEPROM Register
Address: SELECT 00h
Name: Interface Configuration Register 0
Type: Read/Write
Table 11. Interface Configuration Register: Address 00h
Bit Placement Bit Name Description
Bits 1–0
Set Internal
Internal Clock Divider. On Power-On Reset, clock divide-
by-32 selects the Master Clock. On Power-On Reset, set
these bits to 0 0. Table 12 describes Master Clock
Settings.
Bit 1
Bit 0
0
1
1
1
0
1
0
1
Slowest Clock, Clock In divide-by-32
Clock In divide-by-16
Clock In divide-by-4
Clock In
Bits 3–2
EN_OVERIDE
Overrides PCMCIA ATA mode bits, /PC_ATA//HOE
selection on the PCMCIA interface. On Power-On Reset,
both bits are set to 0. Sample /PC_ATA//HOE.
Bit 3
Bit 2
0
0
1
1
0
1
0
1
PC_ATA/HOE Sampled to Set Mode
Forces ATA/IDE Pass Through Mode
Forces PCMCIA Mode
Reserved
PS012002-1201
Programming Internal Registers
ZILOG [ ZILOG, INC. ]
