Z8018x Family
MPU User Manual
71
stacked PC-1. If UFO is 1, the starting address of the invalid instruction is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Restart from 0000H
2nd Op Code
Fetch Cycle
Op Code
Fetch Cycle
PC Stacking
T1 T2 T3
Ti Ti Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
SP-2
PCL
0000H
PC
SP-1
PCH
A0
–
A19
D0
–
D7
Undefined
Op Code
MI
MREQ
RD
WR
Figure 32. TRAP Timing Diagram -2nd Op Code Undefined
UM005001-ZMP0400
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