Z8018x Family
MPU User Manual
198
Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle
except there are no automatica Wait States (TW), and MREQ is active
instead of IORQ.
PHI
32
31
INT0,1,2
NMI
33
M1
30
10
14
28
IORQ
Dat a IN
MREQ
29
15
16
39
40
42
41
RFSH
35
34
35
34
BUSREQ
37
36
38
BUSACK
38
A19–0, D7–0
MREQ, RD
WR, IORQ
Output Buffer Off
43
44
HALT
Figure 82. AC Timing Diagram 2
UM005001-ZMP0400