Z8018x Family
MPU User Manual
167
NMI
Acknowledge
1st MC
Op Code Memory Read/
Fetch Cycle Write Cycle
INT0 Acknowledge
1st MC
I/O Read Cycle I/O Write Cycle
T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2
T3 T1 T2 T3 T1 T2 Tw*Tw* T3
Phi
E
M1
MREQ
IORQ
NOTE : MC = Machine Cycle
* Two wait states are automatically inserted
Figure 67. E Clock Timing Diagram (During Read/Write Cycle and
Interrupt Acknowledge Cycle
BUS RELEASE mode
Last
state
TX TX
TX TX
Phi
BUSREQ
BUSACK
E
E
E
E
Figure 68. E Clock Timing in BUS RELEASE Mode
UM005001-ZMP0400
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