Z8018x Family
MPU User Manual
161
Timer Reload Register Channel 1L (RLDR1L: 16H)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Timer Reload Data
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Reload Register Channel 1H (RLDR1H: 17H)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Timer Reload Data
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Control Register (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status. It also controls
enabling and disabling of down counting and interrupts along with
controlling output pin A18/TOUT for PRT1.
Timer Control Register (TCR: 10H)
Bit
7
TIF1
R
6
TIF0
R
5
4
3
TOC1
R/W
0
2
TOC0
R/W
0
1
TDE1
R/W
0
0
TDE0
R/W
0
Bit/Field
R/W
TIE1
R/W
0
TIE0
R/W
0
Reset
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
UM005001-ZMP0400
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