Z8018x Family
MPU User Manual
162
Bit
Position Bit/Field R/W
Value Description
TIF1: Timer Interrupt Flag — When TMDR1
7–6
TIF1–0
R
decrements to 0, TIF1 is set to 1. This generates an
interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0
when TCR is read and the higher or lower byte of
TMDR1 is read. During RESET, TIF1 is cleared to 0.
When TMDR0 decrements to 0, TIF0 is set to 1. This
generates an interrupt request if enabled by TIE0 = 1.
TIF0 is reset to 0 when TCR is read and the higher or
lower byte of TMDR0 is read. During RESET, TIF0 is
cleared to 0.
5–4
3–2
1–0
TIE1–0 R/W
TOC1–0 R/W
TDE1–0 R/W
Timer Interrupt Enable — When TIE1 is set to 1, TIF1
= 1 generates a CPU interrupt request. When TIE1 is reset
to 0, the interrupt request is inhibited. During RESET,
TIE1 is cleared to 0.
When TIE0 is set to 1, TIF0 = 1 generates a CPU interrupt
request. When TIE0 is reset to 0, the interrupt request is
inhibited. During RESET, TIE0 is cleared to 0.
Timer Output Control — TOC1, and TOC0 control the
output of PRT1 using the multiplexed A18/TOUT pin as
shown in Table 23. During RESET, TOC1 and TOC0 are
cleared to 0. This selects the address function for A18/
TOUT. By programming TOC1 and TOC0 the A18/
TOUT pin can be forced HIGH, LOW, or toggled when
TMDR1 decrements to 0. Reference Table 23.
Timer Down Count Enable — TDE1 and TDE0 enable
and disable down counting for TMDR1 and TMDR0
respectively. When TDEn (n = 0, 1) is set to 1, down
counting is executed for TMDRn. When TDEn is reset to
0, down counting is stopped and TMDRn is freely read or
written. TDE1 and TDE0 are cleared to 0 during RESET
and TMDRn does not decrement until TDEn is set to 1.
UM005001-ZMP0400
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