ZL50022
Data Sheet
7.2 Input Bit Sampling Point Programming
In addition to the input bit delay feature, the ZL50022 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input
streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the
sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default
sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
FPi
Sampling Point = 3/4 Bit
Channel 0
6
STi[n]
Last Channel
STIN[n]SMP1-0 = 00
1
5
2
0
7
(2,
4
or 8 Mbps
-
Default)
Sampling Point = 1/4 Bit
Channel 0
Last Channel
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
1
5
6
0
7
Sampling Point = 1/2 Bit
Channel 0
STi[n]
Last Channel
STIN[n]SMP1-0 = 10
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 00
(16 Mbps - Default)
1
5
6
0
7
Sampling Point = 4/4 Bit
Channel 0
Last Channel
STi[n]
STIN[n]SMP1-0 = 11
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 10
(16 Mbps)
1
5
2
6
0
7
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 14 - Input Bit Sampling Point Programming
30
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
