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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
7.3 Output Advancement Programming  
This feature is used to advance the output data of individual output streams with respect to the output frame  
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output  
Control Register 0 - 31 (SOCR0 - 31).  
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output  
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)  
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 47 on page 83. The output bit  
advancement can vary from 0 to 7 bits.  
FPi  
Channel 2  
Last Channel  
Channel 0  
Channel 1  
STio[n]  
7
6
5
4 3  
4
1
6
1
2
2
0
7
7
6
5
7
6
5
4 3  
3
6
5
4 3  
1
0
6
5
0
7
2
1
0
7
2
1
Bit Adv = 0  
(Default)  
Bit Advancement = 1  
Channel 0  
Channel 2  
Last Channel  
Channel 1  
STio[n]  
5
3
1
4 3  
1
4 3  
2
4 3 2  
Bit Adv = 1  
2
0
2
0
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.  
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)  
32  
Zarlink Semiconductor Inc.  
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