ZL38001
Data Sheet
4.0 Register Summary
External Read/Write Address: 00H
Reset Value: 00H
7
6
5
4
3
2
1
0
LIMIT
MUTE_R
MUTE_S
BYPASS
NB-
AGC-
AH-
RESET
Bit
Name
Description
7
LIMIT
When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC
register and when low 2-bit shift mode is disabled. Default limit for Rin and
Sin is 3.14 dBm0.
6
5
4
3
MUTE_R
MUTE_S
BYPASS
NB-
When high, the Rin path is muted to quite code (after the NLP) and when low
the Rin path is not muted.
When high, the Sin path is muted to quite code (after the NLP) and when low
the Sin path is not muted.
When high, the Send and Receive paths are transparently by-passed from
input to output and when low the Send and Receive paths are not bypassed.
When high, Narrowband signal detectors in Rin and Sin paths are disabled
and when low the signal detectors are enabled.
2
1
AGC-
AH-
When high, AGC is disabled and when low AGC is enabled.
When high, the Howling detector is disabled and when low the Howling
detector is enabled.
0
RESET
When high, the power initialization routine is executed presetting all registers
to default values.
This bit automatically clears itself to ’0’ when reset is complete.
Register Table 1 - Main Control Register (MC)
External Read/Write Address:21H
Reset Value: 00H
7
6
5
4
3
2
1
0
P-
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
7
P-
When high, the Exponential weighting function for the adaptive filter is
disabled and when low the weighting function is enabled
6
5
ASC-
NLP-
When high, the Internal Adaptation speed control is disabled and when low
the Adaptation speed is enabled.
When high, the Non Linear Processor is disabled in the Sin/Sout path and
when low the NLP is enabled.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC)
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
