ZL38001
Data Sheet
Bit 7
Bit 6
Bit 5
Sout/Rout (O)
CT
V
tAHZ
tSD
tDD
tBCH
VH
VL
BCLK (I)
V
CT
tSSS
tBCP
tBCL
tSSH
VH
VL
ENA1 (I)
or
V
V
CT
CT
ENA2 (I)
tDIS
tDIH
start of frame
VH
VL
Rin/Sin (1)
Bit 7
Bit 6
Bit 5
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 13 - SSI Data Port Timing
DATA OUTPUT
DATA INPUT
DATA1 (I,O)
V
V
V
CT
CT
CT
tIDS tIDH
tSCH
tODD
tOHZ
VH
SCLK (I)
VL
tCSSI
tSCL
tSCP
tCSH
VH
(
I)
CS
VL
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 14 - INTEL Serial Microport Timing
27
Zarlink Semiconductor Inc.