P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
P_CLK
4.2 CPU Bus Interface:
P1
P3
P2
P4
P6
P8
P_CLK
P_RST#
P15
P16-min
P_D[31:0]
P_ADS#
P_W/R#
P_CS#
P5
P7
CPU Bus Interface –
Output float delay timing
P_CLK
P16-max
P16-min
P9
P10
P12
P_D[31:0]
P_RDY#
P_INT
P_A[11:1]
P_D[31:0]
P17-max
P17-min
P11
P18-max
P18-min
CPU Bus Interface –
Input setup and hold timing
CPU Bus Interface –
Output valid delay timing
-40
-50
-66
Symbol
Parameter
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Note:
P1
P2
P_RST# input setup time
P_RST# input hold time
P_ADS# input set-up time
P_ADS# input hold time
P_W/R# input set-up time
P_W/R# input hold time
P_CS# input set-up time
P_CS# input hold time
13
3.5
13
10
2.5
10
8
2
8
2
8
2
8
2
8
2
8
2
P3
P4
3.5
13
2.5
10
P5
P6
3.5
13
2.5
10
P7
P8
3.5
13
2.5
10
P9
P_A[11:1] input set-up time
P_A[11:1] input hold time
P_D[31:0]# input set-up time
P_D[31:0]# input hold time
P_D[31:0]# output float delay
P_D[31:0]# # output valid delay
P_RDY# output valid delay
P_INT# output valid delay
P10
P11
P12
P15
P16
P17
P18
3.5
13
2.5
10
3.5
2.5
17
17
13
13
10
10
8
CL = 60pf
10
13
CL = 60pf
CL = 20pf
6.5
5
8.5
AC Characteristics -- CPU Bus Interface
© 1998 Vertex Networks, Inc.
26
Rev. 4.5 – February
1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
