PDSP16256/A
SCLK
SCLK
tHS
tHH
tHS
tHH
tCL
tCH
tHH
CCS
CS
CCS
CS
WEN
C15:0
A7:0
WEN
C15:0
A7:0
VALID DATA
VALID ADDRESS
VALID DATA
VALID ADDRESS
(a) Coefficient Write
(b) Control Register Write
Figure. 20 Remote Master setup and hold timings
CLK 1
CLK 2
CLK 9
SCLK
tCD
tCD
VALID ADDRESS
A7:0
VALID ADDRESS
C15:12
CCS
C7:0
tHS tHH
Figure. 21 EPROM load timings
SCLK
tOS tOH
tCL
tCH
tCD
OEN
tCZF
tCVF
HIGH Z
VALID DATA
VALID DATA
F31:0
VALID DATA
VALID DATA
VALID DATA
OUTPUT PINS
tHS tHH
INPUT PINS
Figure. 22 Operating timings
20