MT9196
Data Sheet
control bits reside in Control Register 1 at address 0Eh. When either of these bits are low their respective paths
function normally. The -Zero entry of Table 1 is used for the quiet code definition.
ST-BUS Mode
The ST-BUS consists of output (DSTo) and input (DSTi) serial data streams, in FDI these are named Dout and Din
respectively, a synchronous clock input signal CLOCKin (C4i), and a framing pulse input (F0i). These signals are
direct connections to the corresponding pins of Zarlink basic rate devices. Note that in ST-BUS mode the XSTL2
pin is not used. The CSL1 and CSL0 bits, as described in the SSI Mode section, are also ignored since the data
rate is fixed for ST-BUS operation. However, the Asynch/Synch bit must be set to logic “0” for ST-BUS operation.
The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s
bandwidth. A frame pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the
32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. A valid frame
begins when F0i is logic low coincident with a falling edge of C4i. Refer to Figure 12 for detailed ST-BUS timing. C4i
has a frequency (4096 kHz) which is twice the data rate. This clock is used to sample the data at the 3/4 bit-cell
position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i is also used to clock the IDPC
internal functions (i.e., Filter/CODEC, Digital gain and tone generation) and to provide the channel timing
requirements.
The IDPC uses only the first four channels of the 32 channel frame. These channels are always defined, beginning
with Channel 0 after the frame pulse, as shown in Figure 7 (ST-BUS channel assignments).
The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (FDI Control Register,
address 10h). ISDN basic rate service (2B+D) defines a 16kb/s signalling (D) Channel. IDPC supports transparent
access to this signalling channel. ST-BUS basic rate transmission devices, which may not employ a microport,
provide access to their internal control/status registers through the ST-BUS Control (C) Channel. IDPC supports
microport access to this C-Channel.
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit and receive) data is provided through an 8-bit read/write
register (address 15h) D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame
for 16 kb/s operation (1 bit/frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the
microport, valid access to this register is controlled through the use of an interrupt (IRQ) output. D-Channel access
is enabled via the (DEn) bit.
DEn:
When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/out of the D-
channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel
timeslot and IRQ outputs are tri-stated (default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/frame (8 kb/s).
When 0, D-Channel data is shifted at the rate of 2 bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of D-
Channel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame,
during which the microprocessor D-Channel read and write operations are performed, then:
a. A microport read of address 15 hex will result in a byte of data being extracted which is composed of four
di-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits
received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 8a: di-bit I is mapped from frame n-
3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from
frame n.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
