MT9196
Data Sheet
port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication
is possible in IDPC. The micro must discard non-valid data which it clocks in during a valid write transfer to IDPC.
During a valid read transfer from IDPC data simultaneously clocked out by the micro is ignored by IDPC.
All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address
byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration
of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the IDPC that a microport
transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive
the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing
whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles
are used to transfer the data byte between the IDPC and the microcontroller. At the end of the two-byte transfer CS
is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which
will remain tri-stated as long as CS is high.
Intel processors utilize least significant bit first transmission while Motorola/National processors employ most
significant bit first transmission. The IDPC microport automatically accommodates these two schemes for normal
data bytes. However, to ensure timely decoding of the R/W and address information, the Command/Address byte is
defined differently for Intel operation than it is for Motorola/National operation. Refer to the relative timing diagrams
of Figures 5 and 6.
Receive data is sampled on the rising edge of SCLK while transmit data is made available concurrent with the
falling edge of SCLK.
Detailed microport timing is shown in Figure 15.
COMMAND/ADDRESS
➄
➀
DATA INPUT/OUTPUT
➀
➃
COMMAND/ADDRESS:
DATA 1
RECEIVE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
DATA 1
TRANSMIT
SCLK
y
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CS
➂
➀
Delays due to internal processor timing which are transparent to IDPC.
➃
➂
y
The IDPC:- latches received data on the rising edge of SCLK.
- outputs transmit data on the falling edge of SCLK.
➂
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
➃
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7
➄
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
X
X
A
4
A
3
A
2
A
1
D
0
A
0
R/W
Figure 5 - Serial Port Relative Timing for Intel Mode 0
11
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