MT9196
Data Sheet
register 2, address 0Fh). This gain adjustment is in addition to the programmable gain provided by the
receive filter and Digital Gain circuit.
•
•
The loudspeaker outputs, pins SPKR+/SPKR-. This internally compensated, fully differential output driver is
capable of directly driving 6.5v p-p into a 40 ohm load.
The Auxiliary Port provides an analog I/O, pins AUXin and AUXout, for connection of external equipment to
the CODEC path as well as allowing access to the speaker driver circuits.
•
•
•
AUXin is a single ended high impedance input (>10 Kohm). This is a self-biased input with a maximum
input range of 2.5vp-p. Signals should be capacitor-coupled to this input.
AUXout is a buffered output capable of driving 40 Kohms//150 pF. Signals for this output are derived from
the receive path or from the AUXin and transmit microphones.
Auxiliary port path gains are:
AUXin to Dout
Din to AUXout
AUXin to AUXout
AUXin to HSPKR±
AUXin to SPKR±
11 dB
20.3 dB
-12 dB
-7.0 dB
-1.1 dB
1.4 dB
5.0 dB
TxINC=0
TxINC=1
RxINC=0
RxINC=1
Refer to the application diagrams of Figures 10 and 11 for typical connections to this analog I/O section.
HSPKR +
75
Ω
IDPC
150 ohm
load
(speaker)
75
Ω
HSPKR -
Figure 4 - Handset Speaker Driver
Microport
The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National
Semiconductor Microwire specifications provides access to all IDPC internal read and write registers. This
microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a
synchronous data clock pin (SCLK).
The microport dynamically senses the state of the serial clock each time chip select becomes active. The device
then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National
requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is
defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during
chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must
be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual
10
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