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MT88E45B 参数 Datasheet PDF下载

MT88E45B图片预览
型号: MT88E45B
PDF下载: 下载PDF文件 查看货源
内容描述: 4线来电号码Identi网络阳离子电路2 [4-Wire Calling Number Identification Circuit 2]
分类和应用:
文件页数/大小: 28 页 / 491 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT88E45B  
Data Sheet  
Line Reversal  
‘Idle State Tone Alert Signal’  
DT-AS  
B
Ch. seizure  
D
Mark  
E
Data  
F
Ring  
A/B Wires  
A
C
G
Note 4  
PWDN  
Note 6  
50-150ms  
Tip/Ring  
CASen  
Note 6  
tDP  
tDA  
EST  
tGP  
tGA  
VTGt  
Note 1  
Note 2  
ST/GT  
tREC  
tABS Note 3  
STD  
Note 7  
15±1ms  
< 0.5mA (optional)  
TE DC load  
TE AC load  
<120µAµ  
20±5ms  
Current wetting pulse (see SIN227)  
Zss (Refer to SIN227)  
Note 4  
Note 5  
FSKen  
Note 6  
tCP  
tCA  
A 100ms  
B = 88-110ms  
C 45ms (up to 5sec)  
D = 80-262ms  
CD  
DR  
Note 7  
E = 45-75ms  
F 2.5sec (typ. 500ms)  
G > 200ms  
DCLK  
DATA  
OSC2  
..101010..  
Data  
Note:  
All  
values  
tPU  
tPD  
obtained from SIN227  
Issue 1  
Figure 17 - Application Timing for BT Caller Display Service (CDS), e.g., CLIP  
Notes:  
1) The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time. VTGt  
is the comparator threshold (refer to Figure 5 for details).  
2) The total tone absent time is tABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time. VTGt  
is the comparator threshold (refer to Figure 5 for details).  
3) By choosing tGA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the STD rising  
edge.  
4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD  
returning to high. The MT88E45B may also be powered down at this time.  
5) The MT88E45B should be taken out of FSK mode when FSK is not expected to prevent the FSK demodulator from reacting to other  
in-band signals such as speech, DT-AS/CAS and DTMF tones.  
6) PWDN, Tip/Ring CASen, FSKen are internal signals decoded from CB0/1/2.  
7) This signal represents the mode of the DR/STD pin.  
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