Data Sheet
MT88E45B
start
start
start
TIP/RING
b7
stop
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
start
b0 b1 b2 b3 b4 b5
(A/B) WIRES
stop
stop
tIDD
start
start
DATA
b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3
(Output)
stop
stop
stop
DCLK
(Output)
tCL
tCH
tCRD
1/fDCLK0
DR
(Output)
tRL
Figure 13 - 3-Wire FSK Data Interface Timing (Mode 0)
Word N+1
3
Word N
7
Demodulated Data
(Internal Signal)
1
5
stop
stop
0
3
2
4
6
7
stop
tRL
Note 2
start
Note 1
DR (Data Ready)
(Output)
>tDDS
>tDDH
1/fDCLK1
DCLK (Data Clock)
(Schmitt Input)
DATA
7
Word N-1
0
1
2
4
5
6
7
stop
0
(Output)
Word N
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
Figure 14 - 3-Wire FSK Data Interface Timing (Mode 1)
21
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