MT8888C
Data Sheet
5.0 VDC
5.0 VDC
MMD6150 (or
equivalent)
2.4 kΩ
3 kΩ
TEST POINT
TEST POINT
130 pF
24 kΩ
100 pF
MMD7000 (or
equivalent)
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 16 - Test Circuits
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after power up.The
initialization procedure should be implemented 100ms after power up.
Description:
Control
Data
b2
X
RS0
1
WR
1
RD
0
b3
X
0
b1
X
0
b0
X
0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
1
0
1
0
1
0
1
0
0
0
0
1
0
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
X
X
X
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
WR
RD
b3
b2
b1
b0
1) Write to Control Register A
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
1
0
1
1
1
0
1
1
0
0
0
1
1
0
0
0
1
0
1
0
1
4) Wait for an interrupt or poll Status Register
5) Read the Status Register
1
1
0
1
X
0
X
1
X
0
X
1
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
0
0
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
1
0
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
0
1
0
0
1
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE
DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO
200 ms (± 4 ms).
Figure 17 - Application Notes
16
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
