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MT8888C 参数 Datasheet PDF下载

MT8888C图片预览
型号: MT8888C
PDF下载: 下载PDF文件 查看货源
内容描述: 集成双音多频收发器与英特尔微型接口 [Integrated DTMF Transceiver with Intel Micro Interface]
分类和应用:
文件页数/大小: 25 页 / 537 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8888C  
Data Sheet  
BIT  
NAME  
DESCRIPTION  
b0  
BURST  
Burst Mode Select. A logic high deactivates burst mode; a logic low enables burst mode.  
When activated, the digital code representing a DTMF signal (see Table 1) can be written  
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal  
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -  
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been  
enabled.  
When CP mode (control register A, b1) is enabled the normal tone burst and pause  
durations are extended from a typical duration of 51 msec to 102 msec.  
When BURST is high (deactivated) the transmit tone burst duration is determined by the  
TOUT bit (control register A, b0).  
b1  
b2  
b3  
TEST  
S/D  
Test Mode Control. A logic high enables the test mode; a logic low deactivates the test  
mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the  
signal present on the IRQ/CP pin will be analogous to the state of the DELAYED  
STEERING bit of the status register (see Figure 7, signal b3).  
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low  
selects the dual tone (DTMF) output. The single tone generation function requires further  
selection of either the row or column tones (low or high group) through the C/R bit (control  
register B, b3).  
C/R  
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects  
a row tone output. This function is used in conjunction with the S/D bit (control register B,  
b2).  
Table 7 - Control Register B Description  
BIT  
NAME  
STATUS FLAG SET  
STATUS FLAG CLEARED  
b0  
IRQ  
Interrupt has occurred. Bit one  
(b1) or bit two (b2) is set.  
Interrupt is inactive. Cleared after  
Status Register is read.  
b1  
TRANSMIT DATA  
REGISTER EMPTY  
(BURST MODE ONLY)  
Pause duration has terminated  
and transmitter is ready for new  
data.  
Cleared after Status Register is  
read or when in non-burst mode.  
b2  
b3  
RECEIVE DATA REGISTER  
FULL  
Valid data is in the Receive Data  
Register.  
Cleared after Status Register is  
read.  
Set upon the valid detection of  
the absence of a DTMF signal.  
Cleared upon the detection of a  
valid DTMF signal.  
DELAYED STEERING  
Table 8 - Status Register Description  
14  
Zarlink Semiconductor Inc.