Data sheet
MH89790B
AC Electrical Characteristics† - Multiframe Clock Timing (Figure 21)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
2
3
4
Receive Multiframe Output Delay
Transmit Multiframe Setup Time
Transmit Multiframe Hold Time
Tx Multiframe to C2 Setup Time
tRMFD
tTMFS
tTMFH
tMF2S
150
ns
ns
ns
ns
50pF
50
50
*
100
† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* 256 tP20 - 100ns
Frame 15
Bit 5 Bit 4
Frame 0
Bit 5 Bit 4
DSTo
Bit Cells
Bit 7
Bit 6
Bit 0
Bit 7
Bit 6
Bit 0
Bit 7
F0i
C2i
RxMF
Figure 19 - Functional Timing for Receive Multiframe Clocks
Frame N
Bit 5 Bit 4
Frame 0
Bit 4
DSTi
Bit 7
Bit 6
Bit 0
Bit 7
Bit 6
Bit 5
Bit 0
Bit 7
Bit Cells
F0i
C2i
TxMF
Figure 20 - Functional Timing for Transmit Multiframe Clock
F0i
C2i
tRMFD
tRMFD
RxMF(1)
TxMF(1)
tMF2S
tTMFH
tTMFS
Figure 21 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams
Note 1: These two signals do not have a defined phase relationship
Zarlink Semiconductor Inc.
23
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
