MH89790B
Data sheet
AC Electrical Characteristics† - ST-BUS Timing (Figures 17 and 18)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
C2i Clock Period
tP20
tW20
tFPS
tFPH
tFPW
tSOD
tSIS
400
200
50
488
244
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
C2i Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
tP20 = 488 ns
150
50
100
300
125
Serial Output Delay
150 pF Load
Serial Input Setup Time
Serial Input Hold Time
Frame Pulse Setup Time 2
30
55
20
tSIH
tFPS2
† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
F0i
C2i
ST-BUS
BIT CELLS
Channel 31
Bit 0
Channel 0
Bit 7
Channel 0
Bit 6
Figure 17 - Clock & Frame Alignment for 2048 kbit/s ST-BUS Streams
ST-BUS
Bit Stream
Bit Cell
tFPW
VIH
F0i
C2i
VIL
tP20
tFPS2
tFPH
tFPS
tW20
tW20
VIH
VIL
tSIS
tSIH
DSTi
or
VIH
VIL
CSTi0/1
tSOD
VOH
VOL
DSTo
or
CSTo
Figure 18 - Clock & Frame Timing for 2048 kbit/s ST-BUS Streams
22
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
