MDS105
MDS105 Physical Pinout
LA_[6]
VSS
L_A[5]
L_A[4]
L_A[3]
L_A[18]
VDD
L_D[31]
L_D[30]
L_D[29]
VSS (CORE)
L_D[28]
L_D[27]
L_D[26]
VDD
L_D[25]
L_D[24]
L_D[23]
L_D[22]
VSS
L_D[21]
L_D[20]
L_D[19]
L_D[18]
VDD (CORE)
L_D[17]
L_D[16]
L_D[15]
VSS
L_D[14]
L_D[13]
L_D[12]
L_D[11]
VDD
L_D[10]
L_D[9]
L_D[8]
VSS (CORE)
L_D[7]
L_D[6]
L_D[5]
L_D[4]
VDD
L_D[3]
L_D[2]
L_D[1]
VSS
L_D[0]
L_A[15]
VDD(CORE)
L_A[16]
L_ADSC#
208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158
2
4
6
8
10
12
14
16
Data Sheet
L_A[7]
L_A[8]
VDD_CORE
L_A[9]
L_A[10]
L_A[11]
VSS
L_A[12]
L_A[13]
L_A[14]
VDD
NC
NC
NC
NC
NC
NC
VSS (CORE)
M0_TXEN
M0_TXD[0]
M0_TXD[1]
M0_CRS_DV
M0_RXD[0]
M0_RXD[1]
VDD
M1_TXEN
M1_TXD[0]
M1_TXD[1]
M1_CRS_DV
M1_RXD[0]
M1_RXD[1]
VSS
NC
NC
NC
NC
NC
NC
VSS (CORE)
NC
NC
NC
NC
NC
NC
VSS(CORE)
NC
NC
NC
NC
NC
NC
156
154
152
+
Pin 1 I.D.
Buffer Mem Interface
Config Interfaces
150
148
146
144
142
140
138
136
134
132
130
128
126
124
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
RMII Port Interfaces
18
122
120
118
116
114
112
110
108
RMII Port Interfaces
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98 100 102 104
106
L_OE#
L_WE#
VSS
L_CLK
VDD
L_A[17]
L_A[2]
VSS
SCLK
VDD
MIR_CTL[3]
MIR_CTL[2]
MIR_CTL[1]
MIR_CTL[0]
RSTIN#
RSTOUT#
VSS(CORE)
T_MODE
TSTOUT[7]
TSTOUT[6]
TSTOUT[5]
TSTOUT[4]
TSTOUT[3]
TSTOUT[2]
TSTOUT[1]
TSTOUT[0]
VDD (CORE)
ACK
DATA0
STROBE
TRUNK_EN
TEST#
SDA
SCL
M_MDIO
VSS
M_MDC
VDD
M4_REFCLK
VSS
M4_SPEED
M4_DUPLEX
M4_LINK
M4_TXD[3]
M4_TXD[2]
M4_TXD[1]
M4_TXD[0]
M4_TXEN
VDD
M4_TXCLK
VSS (CORE)
M4_RXD[3]
NC
NC
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
VDD (CORE)
M2_TXEN
M2_TXD[0]
M2_TXD[1]
M2_CRS_DV
M2_RXD[0]
M2_RXD[1]
VSS (CORE)
M3_TXEN
M3_TXD[0]
M3_TXD[1]
M3_CRS_DV
M3_RXD[0]
M3_RXD[1]
VDD
NC
NC
NC
NC
NC
NC
VSS
M_CLK
VDD (CORE)
M4_RXDV
M4_COL
VSS
M4_RXCLK
VDD
M4_RXD[0]
M4_RXD[1]
M4_RXD[2]
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
