MDS105
1.0
Functional Operation
Data Sheet
The MDS105 is designed to provide a cost effective layer 2 switching solution, using technology from the Zarlink
family to offer a highly integrated product for the unmanaged, Differentiated Services (DS) ready, Ethernet switch
market.
Five 10/100 Media Access Controllers (MAC) provide the protocol interface. These MACs perform the required
packet checks to ensure that each packet that is provided to the Frame Engine has met all the IEEE 802.1
standards. Each MAC supports half duplex “back pressure,” and full duplex 802.3x “PAUSE” Flow Control.
The PHY addresses for the 4 RMII MACs are from 08h to 0Bh. These four ports are denoted as ports 0 to 3. The
PHY address for the uplink MAC is 10 h. This port is denoted as Port 4.
Data packets longer than 1518 (1522 with VLAN tag) bytes and shorter than 64 bytes are dropped, and the
MDS105 is designed to support minimum interframe gaps between incoming packets.
The Frame Engine (FE) is the primary packet buffering and forwarding engine within the MDS105. As such, the FE
controls the storage of packets into and out of the external frame buffer memory, keeps track of frame buffer
availability, and schedules packet transmissions. While packet data is being buffered, the FE extracts the necessary
information from each packet header and sends it to the Search Engine for processing. Search results returned to
the FE initiate the scheduling of packet transmission. When a packet is chosen for transmission, the FE reads the
packet from external buffer memory and places it in the output FIFO of the output port.
2.0
Address Learning and Aging
The MDS105 is able to begin address learning and packet forwarding shortly after power up is completed. The
Search Engine examines the contents of its internal Switch Database Memory for each valid packet that is received
on a MDS105 input port.
Unknown source and destination MAC addresses are detected when the Search Engine does not find a match
within its database. These unknown source MAC addresses are learned by creating a new entry in the switch
database memory, and storing the necessary resulting information in that location. Subsequent searches to a
learned destination MAC address will return the new contents of that MAC Control Table (MCT) entry.
After each source address search the MCT entry aging flag is updated. MCT entries that have not been accessed
during a user configurable time period (1 to 67,108 seconds) will be removed. This aging time period can be
configured using the 16 bit value stored in the registers MAC Address Aging Timer Low and High (AGETIME_LOW,
AGETIME_HIGH). The aging period is defined as the bit concatenation of AGETIME_HIGH with AGETIME_LOW,
multiplied by 1024 ms. For example, if AGETIME_LOW = 25, and AGETIME_HIGH = 01 (in hexadecimal), then the
concatenated value 125 is equal to decimal 293. Multiplying 293 by 1024 ms, we determine that the corresponding
aging time is 300 ms. In fact, 300 ms is the default aging time for the MDS105.
The aging of all MCT entries is checked once during each time period. If the MCT entry has not been exercised
before the end of the next time period, it will be deleted.
3.0
Quality of Service
The MDS105 applies Zarlink’s architecture to provide new Quality of Service (QoS) capabilities for unmanaged
switch applications. Similar to the QoS capabilities of other Zarlink chipset members, the MDS105 offers two
transmit queues per output port.
The Frame Engine (FE) manages the output transmission queues for all MDS105 ports. Once the destination
address search is complete, and the switch decision is sent back to the FE, the packet is inserted into the
appropriate output queue. Whether the packet is inserted into a high or low priority queue is determined by either
the VLAN tag information or the Type of Service/Differentiated Services (TOS/DS) field in the IP header. Either of
these priority fields can be used to select the transmission priority (as per the USE_TOS bit in the FCR register).
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
