MDS105
Unmanaged 5-Port 10/100 Mbps
Ethernet Switch
Data Sheet
Features
•
•
4 10/100 Mbps auto-negotiating RMII ports
1 10/100 Mbps auto-negotiating MII/serial port
(Port 4) that can be used as a WAN uplink or as a
5th port
External I
2
C EEPROM for power-up configuration
-
•
•
•
Default mode allows operation without external
EEPROM
•
November 2003
Ordering Information
MDS105AL
208 Pin PQFP
•
-40°C to +85°C
Provides port-based prioritization of packets on up
to 2 ports (0-1)
-
-
•
•
Input ports are defined to be high or low priority
Allows explicit identification of IP Phone ports
Up to 4 port-based VLANs
Full wire-speed layer 2 switching on all ports (up
to 1.448 M packets per second)
Internal 1 k MAC address table
-
-
Auto address learning
Auto address aging
Ports 0 & 1 can be trunked to provide a 200 Mbps
link to another switch or server
Utilizes a single low-cost external Pipelined,
SyncBurst SRAM (SBRAM) for buffer memory
-
256 k bytes or 512 k bytes (1 chip)
Provides back pressure for half duplex
802.3x flow control for full duplex
Flow Control capabilities
-
-
•
Leading edge QoS capabilities provided based on
802.1p and IP TOS/DS field
-
-
2 queues per output port
Packet scheduling based on Weighted Round-
Robin (WRR) and Weighted Random Early
Detection/Drop (WRED)
Without flow control can drop packets during
congestion using WRED
2 levels of packet drop provided
•
•
•
•
Special power-saving mode for inactive ports
Ability to support WinSock2.0 and Windows2000
smart applications
Transmit delay control capabilities
-
-
Provides maximum delay guarantee (<1 ms)
Supports mixed voice-data networks
-
-
•
•
•
Supports both Full/Half duplex ports
Supports external parallel port for configuration
updates
Port 3 can be used to mirror traffic from the other
3 ports (0-2)
•
Optimized pin-out for easy board layout
S
S
R
A
M
RMII
MDS105
5-Port
Switch
Chip
MII
10/100
Phy
Quad
10/100
Phy
Figure 1 - System Block Diagram
1
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