欢迎访问ic37.com |
会员登录 免费注册
发布采购

MAR2901FBXXX 参数 Datasheet PDF下载

MAR2901FBXXX图片预览
型号: MAR2901FBXXX
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor,]
分类和应用: 外围集成电路微处理器时钟
文件页数/大小: 13 页 / 261 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号MAR2901FBXXX的Datasheet PDF文件第1页浏览型号MAR2901FBXXX的Datasheet PDF文件第2页浏览型号MAR2901FBXXX的Datasheet PDF文件第3页浏览型号MAR2901FBXXX的Datasheet PDF文件第5页浏览型号MAR2901FBXXX的Datasheet PDF文件第6页浏览型号MAR2901FBXXX的Datasheet PDF文件第7页浏览型号MAR2901FBXXX的Datasheet PDF文件第8页浏览型号MAR2901FBXXX的Datasheet PDF文件第9页  
MA2901  
This multiplexer scheme gives the capability of selecting  
various pairs of the A, B, D, Q and “0” inputs as source  
operands to the ALU. These five inputs, when taken two at a  
time, result in ten possible combinations of source operand  
pairs. These combinations include AB, AD, AQ, A0, BD, BQ,  
B0, DQ, D0 and Q0. It is apparent the AD, AQ and A0 are  
somewhat redundant with BD, BQ and B0 in that if the A  
address and B address are the same, the identical function  
results. Thus, there are only seven completely non-redundant  
sourced operand pairs for the ALU. The MA2901  
microprocessor implements eight of these pairs. The  
microinstruction inputs used to select the ALU source  
operands are the l0, I1, and I2 inputs. The definition of l0, I1, and  
I2 for the eight source operand combinations are as shown in  
figure 2. Also shown is the octal code for each selection.  
The two source operands not fully described as yet are the  
D input and Q input. The D input is the four-bit wide direct data  
field input. This port is used to insert all data into the working  
registers inside the device. Likewise this input can be used in  
the ALU to modify any of the internal data files. The Q register  
is a separate 4-bit file intended primarily for multiplication and  
division routines but it can also be used as an accumulator or  
holding register for some applications.  
The ALU itself is a high speed arithmetic/logic operator  
capable of performing three binary arithmetic and five logic  
functions. The I3, I4, and I5 microinstruction inputs are used to  
select the ALU function. The definition of these inputs is shown  
in Figure 3. The octal code is also shown for reference. The  
normal technique for cascading ALU of several devices is in a  
look-ahead carry mode. Carry generate, GN, and carry  
propagate, PN, are outputs of the device for use with a carry-  
look-ahead-generator. A carry-out Cn + 4, is also generated  
and is available as an output for use as the carry flag in a  
status register. Both carry-in (Cn) and carry-out (Cn+4) are  
active HIGH.  
The ALU has three other status-oriented outputs. These  
are F3, F=0, and overflow (OVR). The F3 output is the most  
significant (sign) bit of the ALU and can be used to determine  
positive or negative results without enabling the three-state  
data outputs. F3 is non-inverted with respect to the sign bit  
output Y3. The F = 0 output is used for zero detect. It is an  
open-collector output and can be wire OR’ed between  
microprocessor slices. F = 0 is HIGH when all F outputs are  
LOW. The overflow output (OVR) is used to flag arithmetic  
operations that exceed the available two’s complement  
number range. The overflow output (OVR) is HIGH when  
overflow exists. That is when Cn + 3 and Cn + 4 are not the  
same polarity.  
The ALU data output is routed to several destinations. It  
can be a data output of the device and it can also be stored in  
the RAM or the Q register. Eight possible combinations of ALU  
destination functions are available as defined by the I6, I7, and  
I8 microinstruction inputs. These combinations are shown in  
figure 4.  
The four-bit data output field (Y) features three-state  
outputs and can be directly bus organised. An output control  
(OEN) is used to enable the three-state outputs. When OEN is  
HIGH, the Y outputs are in the high impedance state.  
A two-input multiplexer is also used at the data output  
such that either the A-port of the RAM or the ALU outputs (F)  
are selected at the device Y outputs. This selection is  
controlled by the I6, I7, and I8 microinstruction inputs.  
As was discussed previously, the RAM inputs are driven  
from a three-input multiplexer. This allows the ALU outputs to  
be entered non-shifted, shifted up one position (x 2) or shifted  
down one position (÷ 2). The shifter has two ports; labeled  
RAM0 and RAM3. Both of these ports consist of a buffer-driver  
with a three-state output and an input to the multiplexer.  
Microcode  
ALU Source  
Operands  
Microcode  
ALU  
Symbol  
Function  
Octal  
Code  
I
I
I
0
Octal  
Code  
I
I
I
3
2
1
5
4
R
S
R + S  
R plus S  
L
L
L
0
1
2
3
4
5
6
7
L
L
L
0
1
2
3
4
5
6
7
A
A
0
C
B
Q
B
A
A
Q
0
S - R  
S minus R  
R minus S  
R OR S  
H
L
L
L
L
L
H
L
R - S  
L
H
H
L
L
H
H
L
R ÚS  
H
L
L
L
H
L
0
RN Ù S  
R Ù S  
R Ñ S  
RN Ñ SN  
RN AND S  
R AND S  
H
H
H
H
H
H
H
H
0
H
L
L
H
L
D
D
D
L
H
H
R EX-OR S  
R EX-NOR S  
H
H
H
H
+ = plus; - = minus; = OR; L = AND; Ñ = EX-OR  
V
Figure 2: ALU Source Operand Control  
Figure 2: ALU Function Control  
3
 复制成功!