MA2901
AC ELECTRICAL CHARACTERISTICS
Read-Modify-Write Cycle (from selection of A,B registers to end of a cycle
Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)
Minimum Clock LOW time
Minimum Clock HIGH time
Minimum Clock Period
40ns
25MHz
20ns
20ns
40ns
Note: 1. These timings are applied during functional tests and are not routinely measured.
Figure 12: Cycle Time and Clock Characteristics
To Output
F
C
+ 4
RAM
Y
G,P
F = 0
OVR
Q0
3
n
0
3
From Input
RAM
65
55
50
65
65
30
-
Q
-
3
A,B Address
D
65
55
60
70
60
45
45
55
55
40
40
50
45
-
60
55
50
-
55
45
-
70
65
55
70
65
-
65
55
35
55
50
-
50
35
55
50
-
-
-
-
-
30
-
35
C
n
I
I
I
0,1,2
3,4,5
6,7,8
A Bypass ALU(I=2xx)
Clock
-
50
-
55
-
50
-
50
-
55
55
Note: All timings in ns
Figure 13: Combinational Propagation Delays
Input
CP:
Set-up Time
Before H ® L
Hold Time
After H ® L
Set-up Time
Before L ® H
Hold Time
After L ® H
A,B Source Address
B Destination Address
D
25
25
-
5
30
No change
40
-
5
0
No change
-
-
C
n
-
40
0
I
I
I
-
-
10
-
-
-
45
45
0
0
10
10
0,1,2
3,4,5
6,7,8
No change
-
No change
15
RAM
Q
0,3, 0,3
MIL-STD-883, method 5005, subgroups 9, 10, 11
Note: 1. V = 5V±10%, over full operational temperature range
DD
2. CL = 50 pF
Figure 14: Set-up and Hold Times Relative to Clock (CP) Input
8
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