MA8251
1. FUNCTIONAL DESCRIPTION
1.1 GENERAL
The MA8251 is a Universal Synchronous/Asynchronous
Receiver/Transmitter designed for use with the MA31750
microprocessor. Like other l/O devices in a microcomputer
system, its functional configuration is programmed by the
system’s software for maximum flexibility. The MA8251 can
support most serial data techniques in use, including IBM bi-
sync.
In a communication environment, an interface device must
convert parallel format system data into serial format for
transmission, and convert incoming serial data into parallel
system data for reception. The interface device must also
delete or insert bits or characters that are functionally unique to
the communication technique. In essence, the interface should
appear transparent to the CPU for the simple input or output of
byte-oriented system data.
1.6 WRITE STROBE (WRN)
A low on this signal line indicates that the CPU is writing
data or control information to the MA8251. The MA8251 clocks
data into its data input buffers on a rising edge of WRN.
1.7 CONTROL/DATA (CDN)
This input, in conjunction with the WRN and RDN inputs,
informs the MA8251 that the word on the Data Bus is either a
data character, control word or status information.
1 = CONTROL/STATUS; 0= DATA
CDN
0
0
1
1
x
x
RDN
0
1
0
1
1
x
WRN
1
0
1
0
1
x
CSN
0
0
0
0
0
1
ACTION
MA8251 to CPU
CPU to MA8251
Status to CPU
CPU to Control
Bus Tristate
Bus Tristate
1.2 DATA BUS BUFFER
This 3-state, bidirectional, 8-bit buffer is used to interface
the MA8251 to the system data bus. Data is transmitted or
received by the buffer upon execution of OUTput or INput
instructions from the CPU.
Control word, Command words and Status information are
also transferred through the Data Bus Buffer. The Command
Status, Data-in and Data-out registers are separate 8-bit
registers, communicating with the system bus through the
Data Bus Buffer.
This functional block accepts inputs from the system
control bus and generates control signals for overall device
operation. It contains the Control Word Register and
Command Word Register, which store the various control
formats for the device’s functional definition.
Figure 2: Read/Write Control
1.8 CHIP SELECT (CSN)
A low on this input selects the MA8251. No reading or
writing will occur unless the device is selected. When CSN is
high, the Data Bus is in the float state and the RDN and WRN
lines have no effect on the chip.
1.3 RESET
A high on this input forces the MA8251 into idle mode. The
MA8251 will remain at idle until its functional definition is
programmed with a new set of control words. Minimum RESET
pulse width is 6 tcy (clock must be running).
The device can also be put into the idle state by a
command reset operation .
1.9 MODEM CONTROL
The MA8251 has a set of control inputs and outputs which
can be used to simplify the interface to almost any modem.
The modem control signals are general purpose in nature and
can be used for functions other than modem control, if
necessary.
1.4 CLOCK (CLK)
The CLK input is used to generate internal device timing
and is normally connected to the clock generator (OSC) of the
system.
Please note: None of the external inputs or outputs are
referenced to CLK but the frequency of CLK must be greater
than 30 times the Receiver or Transmitter data bit rates.
1.10 DATA SET READY (DSR)
The
DSR
input signal is a general-purpose, 1-bit inverting
input port. Its condition can be tested by the CPU using a
Status Read operation. The
DSR
input is normally used to test
modem conditions such as Data Set Ready.
1.11 DATA TERMINAL READY (DTR)
The
DTR
output signal is a general purpose, 1-bit inverting
output port. It can be set low by programming the appropriate
bit in the Command instruction word. The
DTR
output signal is
normally used for modem control such as Data Terminal
Ready.
1.5 READ STROBE (RDN)
A low on this signal line indicates that the CPU is reading
data or status information from the MA8251. The MA8251
drives output data onto its data bus whilst this signal remains
low.
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