APRIL 1995
MA8251
DS3810-2.4
MA8251
RADIATION HARD PROGRAMMABLE
COMMUNICATION INTERFACE
The MA8251 is based on the industry standard 8251A
Universal Synchronous Asynchronous Receiver/Transmitter
(USART).
The MA8251 is used as a peripheral device and is
programmed by the CPU to operate using virtually any serial
data transmission technique presently in use (including IBM
“bi-sync”). The USART accepts data characters from the CPU
in parallel format and then converts them into a continuous
serial data stream for transmission.
Simultaneously, it can receive serial data streams and
convert them into parallel data characters for the CPU. The
USART signals the CPU whenever it receives a character for
transmission or whenever it receives a character for the CPU.
The CPU can read the complete status of the USART at any
time, including data transmission errors and control signals
such as SYNDET and TxEMPTY.
RD
WR
FEATURES
■ Radiation Hard to 1MRad(Si)
■ Latch Up Free, High SEU Immunity
■ Silicon-on-Sapphire Technology
■ Synchronous 5 - 8 Bit Characters; Internal or External
Character Synchronisation; Automatic Sync Insertion
Figure 1: MA8251 Block Diagram
■ Asynchronous 5 - 8 Bit Characters; Clock Rate - 1, 16 or
64 Times Baud Rate; Break Character Generation, 1 1⁄
2 Stop Bits
2
or
■ All Inputs and Outputs are TTL Compatible
■ Compatible with the MA31750 (MIL-STD-1750A & Draft
MIL-STD-1750B Option 2) Microprocessor
The MA8251 is based on the industry standard 8251A
USART, incorporating the following features:
prevents the transmitter from turning off in the middle of a
word.
6. When external Sync Detect is programmed, Internal Sync
Detect is disabled and an External Sync Detect status is
provided via a flip-flop, which clears itself upon a status read.
7. The possibility of a false sync detect is minimized in two
ways: by ensuring that if double character sync is
programmed, the characters will be continuously detected
and by clearing the Rx register to all 1’s whenever Enter-Hunt
command is issued in Sync mode.
8. When the MA8251 is not selected, the RDN and WRN
lines do not affect the internal operation of the device.
9. The MA8251 Status can be read at any time but the status
update will be inhibited during status read.
1. MA8251 has double-buffered data paths with separate l/O
registers for control status, data in and data out, which
considerably simplifies control programming and minimizes
CPU overhead.
2. In synchronous operations, the Receiver detects and
handles “break” automatically, relieving the CPU of this task.
3. A refined Rx initialisation prevents the Receiver from
starting when in the “break” state, preventing unwanted
interrupts from the disconnected USART.
4. At the conclusion of a transmission, the TxD line will
always return to the marking state unless SBRK is
programmed.
5. Tx Enable logic enhancement prevents a Tx Disable
command from prematurely halting transmission of the
previously written data before completion. The logic also
10. The MA8251 is free from extraneous glitches, providing
higher speed and better operating margins.
11. Synchronous Baud rate is from DC to 64K.
12. Asynchronous Baud rate is from DC to 19.2K.
1
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
