TEST CIRCUITS
Figure 5. Two-to-Four Wire Insertion Loss
ATIP
ATIP
VTX
VTX
RL
2
SLIC
SLIC
VAB
VL
R
RL VAB
RTT
AGND
AGND
RL
2
RRX
RRX
B(RING)
B(RING)
RSN
RSN
V
IL4-2 = 20 log(V AB / VRX
IL2-4 = 20 log(VTX / VAB
BRS = 20 log(V TX / VRX
)
)
)
Figure 6. Four-to-Two Wire Insertion Loss and Four-to-Four Wire Balance Return Signal
ATIP
VTX
SLIC
VAB
RT
RL
AGND
RSN
RRX
B(RING)
VRX
IL4-2 = 20 log(V AB / VRX
)
BRS = 20 log(V TX / VRX
)
Figure 7. Longitudinal Balance
ATIP
VTX
1
<<
RL
RL
2
ω
C
SLIC
S1
C
RT
S2
VL
VAB
AGND
RSN
VL
RL
2
RRX
B(RING)
V
S2 Open, S1 Closed
L-T Long. Bal. = 20 log(VAB / VL)
S2 Closed, S1Open
4-L Long. Sig. Gen. = 20 log(V L / VRX
-
)
Le79R101 Data Sheet
15
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
