Le79228
Data Sheet
PIN DESCRIPTIONS
Pin Name
AGND1,
AGND2
Type
Description
Ground
Analog circuitry ground returns
For PCM backplane operation, a logic Low on this pin for 16 or more DCLK cycles resets the sequential logic in
the Le79228 Quad ISLAC device into a known mode. A logic low placed on this pin for less than 15 DCLK cycles
is a chip select and enables serial data transmission into or out of the DIO port. For GCI operation, a logic low on
this pin for 1 µs or longer resets the sequential logic into a known mode. This pin is 5-V tolerant.
CS/RST
Input
Provides data control for MPI interface control. For GCI operation, this pin is device address bit 0. This pin is 5-V
tolerant.
DCLK/S0
Input
DGND1,
DGND2
Ground
Digital ground returns
For PCM backplane operation, control data is serially written into the Le79228 Quad ISLAC device via the DIN pin
with the MSB first. The data clock (DCLK) determines the data rate. For GCI operation, this pin is device address
bit 1. This pin is 5 V tolerant. DIN/S1 is available only on the 80-pin LQFP package.
DIN/S1
Input
For PCM backplane operation, control data is serially written into and read out of the Le79228 Quad ISLAC device
via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate. DIO is high impedance except
when data is being transmitted from the Le79228 Quad ISLAC device under control of CS/RST. For GCI operation,
this pin is device address bit 1. This pin is 5-V tolerant. DIO/S1 is available only on the 64-pin TQFP package.
Input/
Output
DIO/S1
For PCM backplane operation, control data is serially read out of the Le79228 Quad ISLAC device via the DOUT
pin with the MSB first. The data clock (DCLK) determines the data rate. DOUT is high impedance except when
data is being transmitted from the Le79228 Quad ISLAC device under control of CS/RST. This pin is 5-V tolerant.
DOUT is available only on the 80-pin LQFP package.
For the PCM highway, the receive PCM data is input serially through the DRA or DRB pins. The data input is
received every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. The receive
port can receive information for direct control of the VE790 series ISLIC device. This mode is selected in Device
Configuration Register 2 (RTSEN=1, RTSMD=1). When selected, this data is received in an independently
programmable timeslot from the PCM data. For the GCI mode, downstream receive and control data is accepted
on this pin. This pin is 5 V tolerant. The DRB pin is available only on the 80-pin LQFP package.
DOUT
Output
Input
DRA/DD,
DRB
For the PCM highway, the transmit PCM data is transmitted serially through the DXA or DXB pins. The
transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit PCM or 16-bit linear bursts
at the PCLK rate. DXA and DXB are high impedance between bursts and while the device is in the inactive mode.
Can also select a mode (RTSEN= 1, RTSMD=1 or 0 in Device Configuration Register 2) that transmits the
Signaling Register MSB contents first, in an independently programmable timeslot from the PCM data. This data
is transmitted in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is
transferred on this pin. This pin is 5 V tolerant. The DXB pin is available only on the 80-pin LQFP package.
DXA/DU,
DXB
Output
For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an 8 kHz Frame Sync signal
on this pin in conjunction with the PCLK on the PCLK/FS pin (see below). This 8 kHz pulse identifies the beginning
of a frame. The Le79228 Quad ISLAC device references individual timeslots with respect to this input, which must
be synchronized to PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this pin in
conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the data rate is 2 MHz and DCL must
be either 2 or 4 MHz. This pin is 5-V tolerant.
FS/DCL
Input
GS11–
GS14,
GS21–
GS24
Gain select nodes for VILG and VIMT inputs. This node provides a switched tie point to VREF. The GS pins are
available only on the 80-pin LQFP package.
Output
VILG1–
VILG4
VIMT1–
VIMT4
Longitudinal current input from ISLIC device. Voltage generated by RLG is sensed by this pin. Tie pin to VREF if
channel unused.
Input
Input
Metallic current input from ISLIC device. Voltage generated by RMT is sensed by this pin. Tie pin to VREF if
channel unused.
For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt a higher level
processor. Several registers work together to control operation of the interrupt: Signaling and Global Interrupt
Registers with their associated Mask Registers, and the Interrupt Register. See the description at channel
configuration register 6 (Mask) for operation. Logic drive is selectable between open drain and TTL-compatible
outputs.
INT
Output
General purpose, logic input/output connection for each of 4 channels. These control lines can be programmed
as an input or output in the Global I/O Direction Register. When programmed as outputs, they can control an
external logic device. When programmed as inputs, they can monitor external logic circuits. Data for these pins
can be written or read individually (from the channel specific I/O Register) or as a group (from the Global I/O Data
Register). The I/O pins are available only on the 80-pin LQFP package.
Input/
I/O1–I/O4
IREF
Output
External resistor (R
) connected between this pin and analog ground generates an accurate, on-chip reference
REF
Input
current for the A/D's and D/A's on the Le79228 Quad ISLAC device.
9
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
