Le79228
Data Sheet
Figure 17. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero, Clock Slot Zero
27
22
26
25
VIH
VIL
PCLK
23
24
FS
28
30
29
TSCA
DXA
See Note 4
31
32
33
VOH
First
Bit
VOL
35
34
VIH
First
Bit
Second
Bit
DRA
VIL
GCI Timing Specifications
For a 2.048 mHz ± 100 PPM, 4.096 mHz ± 100 PPM, or 8.192 ± 100 PPM operation:
Symbol
Signal
DCL
Parameter
Rise/fall time
Period, FDCL = 2048 kHz
DCL = 4096 kHz
Min
—
Typ
—
Max
60
Unit
t , t
R
F
478
239
498
249
t
DCL
—
DCL
F
t
, t
DCL
FS
Pulse width
90
—
—
—
—
—
—
—
—
—
—
—
60
WH WL
t , t
Rise/fall time
Setup time
R
F
t
tDCL–50
FS
70
50
130
—
SF
ns
t
FS
Hold time
—
—
HF
t
FS
High pulse width
Delay from DCL edge
Delay from FS edge
Data setup
WFH
t
DU
DU
DD
DD
100
150
—
DDC
t
—
DDF
t
20
50
SD
t
Data hold
—
HD
25
Zarlink Semiconductor Inc.
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