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LE79Q2284MVC 参数 Datasheet PDF下载

LE79Q2284MVC图片预览
型号: LE79Q2284MVC
PDF下载: 下载PDF文件 查看货源
内容描述: [PCM Codec, A/MU-Law, 1-Func, CMOS, PQFP80, 12 X 12 MM, 1.40 MM HEIGHT, GREEN, LQFP-80]
分类和应用: PC电信电信集成电路
文件页数/大小: 38 页 / 620 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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Le79228  
Data Sheet  
Microprocessor Interface  
Min and max values are valid for all digital outputs with a 150 pF load. Pictorial definitions for these parameters can be found in  
Figure 14, on page 23 and Figure 15, on page 24.  
No.  
1
Symbol  
tDCY  
Parameter  
Data clock period  
Min  
122  
48  
48  
Typ  
Max  
Unit  
Note  
tDCH  
tDCL  
tDCR  
tDCF  
2
Data clock HIGH pulse width  
Data clock LOW pulse width  
Rise time of clock  
1.  
1.  
3
4
25  
5
Fall time of clock  
25  
tICSS  
tICSH  
tICSL  
tICSO  
tIDS  
tDCY–10  
tDCY–20  
6
Chip select setup time, Input mode  
Chip select hold time, Input mode  
Chip select pulse width, Input mode  
Chip select off time, Input mode  
Input data setup time  
30  
0
7
8tDCY  
8
7.  
9
2000  
25  
30  
30  
0
1., 6.  
tDCY–10  
tDCY–10  
tDCY–10  
tDCH–20  
10  
11  
13  
14  
15  
16  
17  
18  
19  
20  
ns  
tIDH  
Input data hold time  
tOCSS  
tOCSH  
tOCSL  
tOCSO  
tODD  
tODH  
tODOF  
tODC  
Chip select setup time, Output mode  
Chip select hold time, Output mode  
Chip select pulse width, Output mode  
Chip select off time, output Mode  
Output data turn on delay  
Output data hold time  
8tDCY  
35  
35  
35  
2000  
1., 6.  
5.  
3
Output data turn off delay  
Output data valid  
3
3
PCM Interface  
Min and max values are valid for TSCA and TSCB with an 150 pF load and are valid for DXA and DXB with an 80 pF load. Pictorial  
definitions for these parameters can be found on Figure 16, on page 24 and Figure 17, on page 25.  
No.  
22  
23  
24  
25  
26  
27  
Symbol  
tPCY  
Parameter  
PCM clock period  
Min.  
122  
48  
Typ  
Max  
7812.5  
Unit  
Note  
2., 9.  
tPCH  
tPCL  
tPCF  
tPCR  
tFSS  
PCM clock HIGH pulse width  
PCM clock LOW pulse width  
Fall time of clock  
48  
15  
Rise time of clock  
15  
tPCY–30  
FS setup time  
30  
125000-  
3tPCY--30  
tFSH  
28  
FS hold time  
50  
ns  
tTSD  
tTSO  
tDXD  
tDXH  
tDXZ  
tDRS  
tDRH  
tFST  
29  
30  
31  
32  
33  
34  
35  
36  
5
5
40  
3.  
4.  
Delay to TSCX valid  
40  
40  
Delay to TSCX off  
PCM data output delay  
5
PCM data output hold time  
PCM data output delay to high-Z  
PCM data input setup time  
PCM data input hold time  
PCM or frame sync jitter time  
5
40  
10  
25  
5
40  
4.  
tPCY–10  
tPCY–20  
–97  
97  
21  
Zarlink Semiconductor Inc.  
 
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