Le79228
Data Sheet
Master Clock
Master Clock can be sourced by MCLK or PCLK input by appropriate configuration of DCRI (see Figure 13). For a 2.048 mHz ±
100 PPM, 4.096 mHz ± 100 PPM, or 8.192 ± 100 PPM operation:
No.
Symbol
Parameter
Min
Typ
Max
Unit
No
2., 8.,
9.
tMCY
37
Period
122
—
7812
tMCR
tMCF
tMCH
tMCL
38
39
40
41
Rise time of clock
—
—
48
48
—
—
—
—
15
15
—
—
ns
Fall time of clock
Master Clock HIGH pulse width
Master Clock LOW pulse width
Note:
1. DCLK may be stopped in the High or Low state indefinitely without loss of information. When CS makes a transition to the High state, the
last byte received will be interpreted by the Microprocessor Interface logic.
2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK frequency.
The actual PCLK rate is dependent on the number of channels allocated within a frame. A PCLK of 1.544 mHz can be used for standard
US transmission systems. The minimum clock frequency is 128 kHz.
3. TSCX is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock slot register.
4. TSCX is an open drain driver. tTSO is defined as the delay time the output driver turns off after the PCLK transaction. The actual delay time
is dependent on the load circuitry. The maximum load capacitance on TSCX is 150 pF and the minimum pull-up resistance is 360 Ω.
5. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
6. The Le79228 Quad ISLAC device requires 2.0 µs between MPI operations. If the MPI is being accessed while the MCLK (or PCLK if
combined with MCLK) input is not active, a Chip Select Off time of 20 µs is required when accessing coefficient RAM. Immediately after
2µs ⋅ 8.192 MHz
tICSO = -------------------------------------------
reset,
, where fPCLK is the applied PCLK frequency. Once DCR1 is programmed for the applied PCLK and
fPCLK
MCLK, tICSO is per table specification.
7. If chip select is held low for 16 or more DCLK cycles, the part will reset.
8. Master Clock’s frequency can range from 512 kHz to 8.192 MHz and can be set with: Write/Read Device Configuration Register 1, and if
necessary Write/Read Master Clock Correction Register.
9. If PCLK is greater or equal to 512 kHz, the preferred configuration is Master Clock derived from PCLK. If a separate MCLK is used, it must
be synchronous to PCLK. If PCLK is less than 512 kHz, a separate MCLK (synchronous with PCLK) with f0 greater or equal to 512 kHz
must be used.
22
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
