Le79555
Data Sheet
TEST CIRCUIT SCENARIOS
Figure 4. Two-to-Four-Wire Insertion Loss
A (TIP)
VTX
RL
2
SLIC
VAB
RT
VL
AGND
RSN
RL
2
RRX
B (RING)
IL2-4 = 20 log(V TX / VAB
)
Figure 5. Four-to-Two-Wire Insertion Loss and Balance Return Signal
A (TIP)
VTX
SLIC
VAB
RT
RL
AGND
RSN
RRX
B (RING)
VRX
IL4-2 = 20 log(V AB / VRX
)
BRS = 20 log(V TX / VRX
)
Figure 6. Longitudinal Balance
VTX
A (TIP)
1
<<
RL
RL
2
ω
C
SLIC
S1
C
RT
S2
VL
VAB
AGND
RL
2
RRX
B (RING)
RSN
VRX
S2 Open, S1 Closed
S2 Closed, S1Open
L-T Long. Bal. = 20 log(V AB / VL)
L-4 Long. Bal. = 20 log(V TX / VL)
4-L Long. Sig. Gen. = 20 log(V L / VRX)
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
