Le79555
Data Sheet
Loop Detector
Description
Test Conditions (See Note 1)
= 35.4 kΩ
Min
9.4
8.8
Typ
11.7
10.4
1.3
Max
14.0
12.0
Unit
Note
R
R
R
Off-hook threshold
D
D
D
= 35.4 kΩ
= 35.4 kΩ
On-hook threshold
Hysteresis
mA
RL from BX to GND
Active, Standby, and Tip open
IGK, Ground-key detector threshold
5
9
13
Relay Driver Output
(RINGOUT, RYOUT1, RYOUT2)
Description
Test Conditions (See Note 1)
IOL = 40 mA
Min
Typ
+0.3
Max
+0.7
100
Unit
V
Note
On voltage
V
OH = +5 V
Off leakage
µA
IZ = 100 µA
IZ = 30 mA
Zener breakover
Zener On voltage
6
7.2
8
V
Figure 1. Relay Driver Schematic
RINGOUT,
RYOUT1, RYOUT2
BGND
1. Unless otherwise noted, R = 600 Ω. Also, refer to the Le79555 device test circuit in Figure 9, on page 16.
L
2.
a) Overload level is defined as THD = 1%.
b) Overload level is defined as THD = 1.5%.
3. Balance return signal is the signal generated at V by V . This specification assumes that the two-wire, AC-load impedance matches
TX RX
the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7. Group delay can be greatly reduced by using a ZT network such as that shown in Figure 7. The network reduces the group delay to less
than 2 µs and increases 2WRL. The effect of group delay on line card performance also may be compensated for by synthesizing complex
impedance with the QLSLAC™ device.
8. Minimum current level guaranteed not to cause a false loop detect.
11
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
