Le78D11
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
Power
AGND1, AGND2
DGND1, DGND2
VCCA1, VCCA2
VCCD
Analog section ground return for each channel
Digital section ground returns
+3.3 VDC supplies to the analog section in each channel
+3.3 VDC supply to all digital sections
PCM Interface
PCM mode, the receive PCM data is input serially through the DRA pin. The data input is received
every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. For
the GCI mode, downstream receive and control data is accepted on this pin.
For the PCM highway, the transmit PCM data is transmitted serially through the DXA pin. The
transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit PCM or
16-bit linear bursts at the PCLK rate. DXA is high impedance between bursts and while the device
is in the inactive mode. For the GCI mode, upstream transmit and signaling data is transferred on
this pin.
DRA/DD
DXA/DU
Input*
Output*
For PCM operation, this pin functions as the Frame Sync input. PCM operation is selected by the
presence of an 8 kHz Frame Sync signal on this pin in conjunction with the PCLK (see below).
This 8 kHz pulse identifies the beginning of a frame. The Le78D11 VoSLAC device references
individual time slots with respect to this input, which must be synchronized to PCLK. In GCI mode,
the rate at which data is shifted into or out of the pin is a derivative of this DCL clock.
For PCM backplane operation, a DSP master clock is connected to this pin. A signal is required
only for PCM backplane operation when PCLK is not used as the master clock. MCLK can be a
wide variety of frequencies. Upon initialization the MCLK input is disabled, and relevant circuitry
is driven by PCLK. The MCLK connection is established under user control. This pin is not used
in GCI mode, and should be tied to ground.
FS/DCL
MCLK
Input*
Input*
For PCM operation, this pin is the PCM Clock input. PCM operation is selected by the presence
of a PCLK signal on this pin in conjunction with the FS on the FS pin (see below). This clock
determines the rate at which PCM data is serially shifted into and out of the PCM ports. PCLK
must be an integer multiple of the FS frequency. The minimum clock frequency for linear/
companded data plus signaling data is 256 kHz. For GCI operation, this pin functions as Frame
Sync. The FSC signal is an 8 kHz pulse that identifies the beginning of a frame. The Le78D11
VoSLAC device references individual time slots with respect to this input, which must be
synchronized to DCL.
PCLK/FSC
Input*
Output
(PCM)
Input
For PCM backplane operation, TSCA is active low when PCM data is output on the DXA pin. The
outputs are open-drain and are normally inactive (high impedance). Pull-up loads should be
connected to VCCD. When GCI mode is selected, one of two GCI modes may be selected by
connecting TSCA/G to DGND or VCCD.
TSCA/G
(GCI)*
MPI Interface
CS
For PCM backplane operation, a logic low placed on this pin enables serial data transmission into,
or out of, the DIN/DOUT pin. Not used in GCI mode (pin should be pulled high in GCI mode).
Data clock for the MPI control interface. For GCI operation, this pin is device address bit 0.
Input*
Input*
DCLK/S0
For PCM backplane operation, control data is serially written into the Le78D11 VoSLAC device
via the DIN pin with the MSB first. The data clock (DCLK) determines the data rate. This pin may
also be tied to DOUT, on systems using a single bi-directional data line (Bit 7 in register DCR2
must be low when DIN is tied to DOUT). For GCI operation, this pin is device address bit 1.
For PCM backplane operation, control data is serially read out of the Le78D11 VoSLAC device
via the DOUT pin with the MSB first. The data clock (DCLK) determines the data rate. This pin
may also be tied to DIN, on systems using a single bi-directional data line (Bit 7 in register DCR2
must be low when DIN is tied to DOUT). This pin is not used in GCI mode, and must remain
unconnected.
DIN/S1
DOUT
Input*
Output*
For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt
a higher level processor. Several registers work together to control operation of the interrupt:
Signaling and Global Interrupt Registers with their associated Mask Registers, and the Interrupt
Register. See the description at configuration register 6 (Mask) for operation. Logic drive is
selectable between open drain and TTL-compatible outputs. In GCI mode, this pin functions as
device address bit 2.
Output
(PCM)
Input
INT/S2
RS
(GCI)*
Input*
Active low reset for the Le78D11 VoSLAC device.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
